Slope or integrating type analog to digital converters (ADCs) have typically been used for high precision averaging type measurements. Integrating ADCs are relatively slow devices having low input bandwidths but combine high resolution and low power consumption while advantageously utilizing the available speed. Additionally, ADCs are able to reject high-frequency noise and fixed low frequencies, which makes them useful in noisy industrial environments and applications where high update rates are not required, such as digitizing the outputs of strain gauges and thermocouplers.
An example of a conventional integrating ADC 100 is shown in FIG. 1. The integrating ADC 100 has two main sections which include an integrating portion 105 for acquiring and integrating an input voltage to produce an integrated voltage signal, and a counter 140 for translating the integrated voltage signal into a digital output value. The integrating portion 105 includes a first switch S1 for switching between an input voltage Vin and a reference voltage Vref. The first switch S1 is connected to an analog amplifier 110 through a resistor R. The output of the analog amplifier 110 is connected to a comparator 120. A capacitor C and a second switch S2 are connected in parallel across the analog amplifier 110. The output of the comparator 120 and a clock signal CLK are input to control logic 130. Responsive to these inputs, control signals from the control logic 130 control the first and second switches S1 and S2 for integrating the input voltage Vin during a fixed integrating time interval (Tcharge) and then de-integrating the reference voltage Vref until the output substantially reaches zero for a time interval (Tdischarge) as shown in FIG. 2.
In the integrating portion 105, the analog amplifier 110 charges the capacitor C with the input voltage Vin (first switch S1 is set to Vin). In the de-integrating portion, the analog amplifier 110 discharges the capacitor C with an opposite-polarity reference voltage Vref (first switch S1 is set to Vref). Vin is integrated for the fixed time interval Tcharge that corresponds to the maximum count of the counter 140. At the end of the fixed time interval Tcharge, the counter 140 is reset and Vref is applied to the input of the analog amplifier 110. The analog amplifier 110 then de-integrates until an output of zero is reached, which defines the end of the time interval Tdischarge, at which point in time the counter 140 is stopped and the analog amplifier 110 is reset (second switch S2 is momentarily closed).
Such ADCs are known to be used as a part of a data acquisition system for computer based systems. In addition to the ADC measurements, further calculations may be performed in the system to correct and improve the measurement accuracy thereof. One such calculation is to correct for a fixed offset in the signal being measured or an offset in the front end of the ADC. When correcting for fixed offsets in the signal being measured, the system can apply two levels of excitation to a device being measured, perform two A/D conversions and then calculate the difference between the two digital conversion values by using a dedicated hardware arithmetic logic unit (ALU) or a processor. One example of such a measurement is for a resistance having a diode or diodes in series therewith which are responsible for the offset.
When correcting for fixed offsets in the front end of the ADC, a zero input is applied, an A/D conversion is performed and then the unknown value is connected to the front end and a second A/D conversion is performed. The difference between the two digital conversion values represents the converted unknown value. Again, an ALU or processor is needed to perform these calculations.
After the offsets have been corrected, additional post processing may be performed to test the values against limits. Again, this can be done in a processor system or with dedicated registers and ALU operations in dedicated logic.
Correcting for ADC offsets in a separate processor or arithmetic logic may be infeasible in certain applications, or may unduly increase the cost and/or complexity of ADC-based measurement circuitry. A system is therefore desirable for eliminating the need for such dedicated ALU hardware or microprocessor/computer support for post processing and A/D offset correction.
The present invention is directed to a system which reduces the reliance on hardware and processor support when correcting for A/D offset by performing a pair of dual slope measurement cycles with an integrating ADC. The integrating ADC performs an initial dual slope measurement cycle to obtain and store a count value, and this count value is then used during a second dual slope measurement to manipulate a counter. As a result of these measurements, the present system automatically performs a difference calculation on the count value during the second measurement cycle. The present system may also realize a direct comparison against limits during the second measurement which eliminates the need for additional hardware and processing support.
According to an embodiment of the present invention, a system is provided for measuring signals in a non-linear network by utilizing an integrating ADC circuit for performing dual slope measurement cycles. Each of the measurement cycles has at least four phases including a first integrating phase for integrating a first excitation voltage for a fixed time interval and generating a first integrated voltage, a first de-integrating phase for de-integrating the first integrated voltage until a predetermined threshold voltage is reached and generating a first digital output value, a second integrating phase for integrating a second excitation voltage for the fixed time interval and generating a second integrated voltage, and a second de-integrating phase for de-integrating the second integrated voltage until the predetermined threshold voltage is reached and generating a second digital output value.
The system further includes an ADC controller operatively communicative with the integrating ADC circuit for obtaining and storing a first count value corresponding to the first digital output value at the end of the first de-integrating phase and obtaining a second count value corresponding to the second digital output value at the end of the second de-integrating phase. The ADC controller detects when the first count value is reached during the second de-integrating phase and resetting the second count value in response to detecting the first count value so that the second count value is offset corrected at the end of the second de-integration phase. As a result, the present invention eliminates the need of dedicated hardware and processing for offset correction and direct comparison against limits for achieving the integration of this system with reduced silicon area and complexity while maintaining performance accuracy.
Other aspects, features and advantages of the present invention are disclosed in the detailed description that follows.